The present invention concerns circuitry for decoding closed-caption information from television signals and more particularly to such circuitry having synchronization features which allow it to operate effectively even in the presence of signal noise.
As of Jul. 1, 1993 every television set sold in the United States having a screen larger than 13" must be capable of decoding and displaying closed-caption information.
Under the standards approved by the Federal Communications Commission (FCC), closed-caption information is text representing dialog or narration from a television program which is encoded in the video portion of the television signal. Two characters of information are transmitted during each image frame, for a data rate of 60 characters per second. Under the present standard, this information is digitally encoded in line 21 of the vertical blanking interval of the odd field of each frame of the video signal.
FIG. 3 is a timing diagram which illustrates the format of line 21 of the odd field. The line includes a horizontal sync pulse (HS), a color reference burst signal, B, seven cycles of a clock run-in signal, a start byte pattern and two bytes of closed-caption data. In FIG. 3, the center of the leading edge of the horizontal sync pulse HS occurs at time T1. The first pulse of the run-in clock occurs at time T2 and the last pulse occurs at time T3. The start byte pattern in this case, b`100` (where the "b" indicates binary notation), is sent least significant bit (LSB) to most significant bit (MSB) between times T3 and T4. The two data bytes are sent between times T4 and T5. The byte beginning at time T4 is, by definition, the less significant byte while the byte ending at time T5 is the more significant byte. In FIG. 3, time T6 marks the beginning of the horizontal sync pulse for line 22.
Each of the data bytes which make up the closed-caption data are eight bits in length with seven bits being for data and the eighth bit being a parity bit. The data bits are sent using a non-return to zero (NRZ) code.
Existing closed-caption decoders recover the data bytes from each frame and display the resulting text in a small window anywhere (e.g., near the bottom) of the image.
The data portion of this signal is desirably sampled at certain predefined instants to ensure that the character data is accurately recovered. Under the FCC closed-caption standard, the NRZ coded data bits are serially transmitted with a sample frequency of 503,488 Hz (hereinafter 503 KHz). This frequency is 32 times the frequency of the horizontal line scanning signal (32 H).
Many prior art closed-caption coding systems use a phase locked loop to produce the 503 KHz clock. An exemplary system of this type is described in an article by M. Harigai et al. entitled "LSI Chip set for closed Caption Decoder System", IEEE Transactions on Consumer Electronics, vol. 37, no. 3, pp. 449-454 (August 1991). This system employs two nested phase lock loops (PLLs). The inner PLL locks a voltage control oscillator (VCO) to a frequency which is 32 times the horizontal line sampling frequency. The outer PLL is responsive to the recovered clock run-in pulses to shift the phase of the 32 H clock signal to match the sampling phase indicated by the clock run-in signal.
Circuits of this type which employ PLLs for synchronization have several disadvantages. First, the sampling clock can be misaligned if the signal is contaminated with multi-path distortion (ghosts). Second, the phase locked loop circuitry and phase shift circuitry can add to the complexity of the decoder, making it more expensive to produce than a decoder which does not employ phase locked loops. Third, noise in one pulse of the run-in clock signal may cause a synchronization error resulting in errors in the recovered data. Finally, it may be difficult to synchronize the decoder to the display processor unless the clock signal for the display processor is at a frequency related to the frequency of the close caption data sampling clock.
Another type of system uses a digital phase lock loop to generate the sampling clock signal. This system is described in a paper by U. Moller et al. entitled "A Single Chip Solution for Closed-Caption Decoding", IEEE Transactions on Consumer Electronics, vol. 38, no. 3, pp. 274-278 (August 1992). In this system a 12 MHz clock signal is alternately divided by five and by seven to produce a signal which has an average frequency of 2.013952 MHz. This frequency is four times the sampling frequency of the closed-caption data. The closed-caption decoder described in this paper over-samples the closed-caption data on line 21 by a factor of four and uses a majority count decision mechanism to determine the state of the individual bits; three of four samples at one logic level produces an output sample at that logic level.
This circuitry requires a relatively large state machine to correlate the sampling frequency to the data being sampled. This state machine must also include features which allow the signal to be recovered properly in the presence of noise. These features add to the expense of the closed caption decoder.